Synopsys delivers comprehensive silicon-to-systems solutions that help innovators accelerate development, reduce risk, and drive breakthroughs. Backed by NEA.
About the role
You have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's or Master's in Electrical Engineering or Computer Engineering with 5+ years of hands-on verification experience for IP cores or SoC designs (or Master's with 3+ years)
- Strong SystemVerilog and HVL coding skills with proven ability to build testbenches, write constrained-random tests, and implement functional coverage
- Direct experience with UVM, VMM, or OVM methodologies applied to real verification projects
- Hands-on proficiency with industry-standard simulators such as VCS, NC (Xcelium), or MTI (Questa) and their associated debugging tools
- Solid understanding of functional coverage and code coverage concepts, and how to use them to drive verification closure
- Experience with Verilog for reading and understanding RTL is highly desired
More about this role
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise. You are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team....
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