Synopsys delivers comprehensive silicon-to-systems solutions that help innovators accelerate development, reduce risk, and drive breakthroughs. Backed by NEA.
About the role
You have spent years deep in the details of digital IC design, and you know that the difference between a chip that works and one that doesn't often comes down to decisions made during DFT planning. You are the engineer who catches those decisions early, who can look at a scan architecture and immediately see where the coverage gaps will show up three months later during silicon bring-up.
What they're looking for
- Bachelor's degree with 7+ years or Master's degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field
- Hands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs
- Deep knowledge of scan architectures, fault models, test access networks, and IEEE standards including 1149.1, 1500, and 1687
- Proven ability to handle scan implementation and validation for large, multi-IP SoCs with complex hierarchies and multiple clock domains
- Experience with MBIST concepts, architecture planning, and integration in automotive or safety-critical design environments is a strong plus
- Familiarity with industry-standard DFT tools and flows, exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable
More about this role
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years deep in the details of digital IC design, and you know that the difference between a chip that works and one that doesn't often comes down to decisions made during DFT planning. You are the engineer who catches those decisions early, who can look at a scan architecture and immediately see where the coverage gaps will show up three months later during silicon bring-up. You have debugged enough ATPG failures and MBIST issues to know that the best solutions start with understanding what the customer is actually trying to build, not just what they think they need.
You operate at the intersection of deep technical work and customer collaboration. You can spend the morning implementing a complex test access network for a multi-IP SoC and...
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