Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in the U.S. with offices in Austin, Texas, and Silicon Valley, and global offices in Toronto, Belgrade, Seoul, Tokyo, and Bangalore, Tenstorrent brings together...
About the role
Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads.
What they're looking for
- Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems
- Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems
- Comfortable making architectural decisions across CPU cluster and subsystems
- Collaborative technical leader who enjoys influencing cross-functional engineering teams
- Curious and driven to solve challenging performance, scalability, and system architecture problems
More about this role
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into...
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