About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. Backed by Matter Venture Partners.
About the role
In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.
What they're looking for
- Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs
- Lead implementation of scan insertion, ATPG, MBIST, boundary scan, SSN implementation, and test compression methodologies
- Drive DFT planning and integration aligned with power, timing, area, and test coverage goals
- Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff
- Analyze and resolve DFT-related timing, routing, and testability challenges
- Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization
More about this role
About the role
We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive end-to-end DFT architecture including scan with compression technologies, MBIST, boundary scan, SSN architecture, functional testing and at-speed test methodologies while collaborating with cross-functional teams to achieve high test coverage, quality, and silicon bring-up success.
What you'll do
- Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
- Lead implementation of scan insertion, ATPG, MBIST, boundary scan, SSN implementation, and test compression methodologies.
- Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
- Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
- Analyze and resolve DFT-related timing, routing, and testability challenges.
- Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
- Develop and enhance DFT automation flows,...
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