About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. Backed by Matter Venture Partners.
About the role
We are seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the verification strategy for our next-generation semiconductor products. In this role, you will lead a team of verification engineers tasked with validating highly complex, multi-million gate SoC designs.
What they're looking for
- Technical Leadership & DV Strategy: Lead, mentor, and grow the verification team. Architect the overall verification environment, defining the standards for testbenches, automation scripts, and regression metrics
- Verification Planning: Translate architectural specifications into comprehensive verification plans. Identify edge cases, corner cases, and critical scenarios that must be stress-tested
- Environment Architecture (UVM): Own and build modular, scalable, and reusable advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Deploy AI-driven verification methodology for SoC Verification
- Advanced Verification Techniques: Deploy formal verification, assertion-based verification (SVA), and hardware/software co-verification where appropriate to accelerate bug discovery
- Signoff Discipline: Track and drive functional coverage, code coverage, and assertion metrics to absolute closure. Define and enforce the official bug-bar and criteria for pre-silicon signoff
More about this role
Role Overview
We are seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the verification strategy for our next-generation semiconductor products. In this role, you will lead a team of verification engineers tasked with validating highly complex, multi-million gate SoC designs. You will work side-by-side with the SoC Front-End Lead and cross functional teams including Emulation and Firmware teams to establish robust methodologies and guarantee first-time-right silicon through rigorous block-level, subsystem, and full-chip verification.
What you'll do
- Technical Leadership & DV Strategy: Lead, mentor, and grow the verification team. Architect the overall verification environment, defining the standards for testbenches, automation scripts, and regression metrics.
- Verification Planning: Translate architectural specifications into comprehensive verification plans. Identify edge cases, corner cases, and critical scenarios that must be stress-tested.
- Environment Architecture (UVM): Own and build modular, scalable, and reusable advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
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