About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. Backed by Matter Venture Partners.
About the role
In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.
What they're looking for
- Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing
- Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR, SerDes interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques
- Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching
- Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design
- Drive DRC/DFM closure with substrate vendors, manage design review cycles through tapeout
- Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection for package robustness
More about this role
Role Overview
TYLsemi is seeking a Package Design Engineer to own design of IC packages (flip-chip, wirebond and 2.5D/interposer platforms) for high-speed digital and data-center-class products. The successful candidate will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout — working closely with SI/PI, silicon design, and test engineering to deliver package designs that are robust against real silicon feedback.
What You’ll Do
- Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing.
- Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR; SerDes interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques.
- Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching.
- Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design.
- Drive DRC/DFM closure with substrate...
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