Upscale builds next-generation AI network infrastructure with scalable systems, intelligent automation, and seamless connectivity.
About the role
Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.
What they're looking for
- BE or MS in EE, CE, CS
- 5+ years of related technical engineering experience
- 5+ years of industry experience in logic design on complex ASICs
- Experience with SystemVerilog for logic design
- Understanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure
- Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
More about this role
Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.
We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.
If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.
- As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.
- Responsible for the logic design/RTL entry that meets the power, performance, area targets.
- Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test...
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