Upscale builds next-generation AI network infrastructure with scalable systems, intelligent automation, and seamless connectivity.
About the role
Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of industry experience, or a Master's degree with 7+ years of relevant experience
- Proven experience verifying complex ASIC designs at both block and system levels
- Strong proficiency with SystemVerilog and the Universal Verification Methodology (UVM)
- Extensive knowledge of ASIC design verification methodologies, verification flows, and industry best practices
- Experience collaborating with cross-functional teams to deliver ASIC products from architecture through first customer shipment (FCS)
- Strong programming and scripting skills in C, C++, and/or Python
More about this role
Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.
We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.
If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.
- Design, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.
- Develop comprehensive verification plans and create test cases to ensure complete functional coverage.
- Verify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based...
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