Backed by MVP Ventures.
About the role
We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
What they're looking for
- 8 or more years verifying high performance compute or complex digital designs
- High level understanding of LLMs including transformer structure and inference data flow
- Knowledge of GEMM and GEMV operations and how they map onto hardware
- Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification
- Experience building or using reference models in C, C++ or Python
- Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8
More about this role
We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
This role focuses on our AI acceleration units. We are designing custom compute engines from scratch to deliver industry leading inference performance at best in class energy efficiency, and every gain has to come inside a tight power envelope. You will own verification of the hardware that makes those numbers real, where correctness means numerical behavior as much as protocol.
- Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
- Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
- Build verification environments using SystemVerilog, UVM, C and C++, with stimulus,...
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