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Design Verification Engineer- CPU

Velaura AI · Santa Clara, CA · On-site

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About Velaura AI

Backed by MVP Ventures.

About the role

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

What they're looking for

  • 8 or more years verifying high performance CPUs or complex digital designs
  • Strong computer architecture and microarchitecture fundamentals
  • Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification
  • Experience owning a block or unit of a design independently from test plan through coverage closure
  • Experience writing test plans, portable testbenches and transactors
  • Experience debugging complex issues across hardware and software boundaries
More about this role

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role focuses on our custom CPU. We are designing a leading edge, high performance processor from scratch, and you will own a functional domain of its verification from test plan through coverage closure, proving that a newly designed microarchitecture behaves as intended.

  • Own verification of custom CPU units including instruction fetch, decode, load store, and the instruction, data and last level caches.
  • Work with CPU and SoC architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans.
  • Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
  • Develop instruction level...

Read the full posting on Velaura AI's site ↗

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