Backed by MVP Ventures.
About the role
We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip.
What they're looking for
- Experience designing RTL for complex digital systems, with hands-on ownership of memory subsystem blocks
- Demonstrated experience integrating a memory controller with a memory PHY, including controller-to-PHY interfaces such as DFI, initialization and training sequences, and bring-up
- Strong understanding of high-speed, low-power memory technologies such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including their protocol, timing, and power-state behavior
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
- Expert-level Verilog and SystemVerilog skills and experience with modern RTL design methodologies, including lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent
- Familiarity with performance, power, and area tradeoffs in the memory path
More about this role
We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip.
In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP and PHY partners to transform innovative architectural concepts into production silicon. You will own significant portions of the memory subsystem design, contribute to microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems.
Physical AI workloads are memory-bound: bandwidth, latency, and power in the memory path directly gate what the chip can do. If pushing modern memory technologies to their limits at high speed and low power is the kind of problem you want to own, this role is for you.
- Design, implement, and optimize RTL for the memory subsystem of the Velaura SoC, including memory controllers, fabric interfaces, and the logic that integrates with external memory PHYs.
- Own memory controller and PHY integration, including controller-to-PHY...
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