Backed by MVP Ventures.
About the role
Velaura is building custom silicon for Physical and Embodied AI, and we are building it from a blank sheet. The automation our design and verification engineers use to get
What they're looking for
- 8 or more years in design verification, design or CAD engineering, including ownership of a flow area
- Strong SystemVerilog and RTL fluency with the ability to read and debug design and testbench code
- Hands on experience building and running simulation and regression flows including testbench compile, coverage collection and results triage
- Excellent Python skills and a track record of building tools that other engineers maintain
- Working knowledge of front end design and verification EDA tools from Synopsys, Cadence or Siemens EDA
- Working knowledge of Linux administration, distributed compute such as LSF or Slurm, and the storage and scaling constraints behind large regression workloads
More about this role
Velaura is building custom silicon for Physical and Embodied AI, and we are building it
from a blank sheet. The automation our design and verification engineers use to get
from RTL to a clean handoff shapes how fast that silicon comes together.
You will own the front end automation that carries our silicon from RTL entry to a clean
handoff into DFT and implementation. The scope covers RTL design flows, verification
flows from simulation through prototyping, and the AI assisted tooling built over them.
Success is measured two ways. Front end engineers get more done, and the tools they
rely on stay up through every phase of the design cycle.
- Own the RTL design flows including build, lint, CDC and formal checks.
- Own register generation and the generator driven flows behind interfaces and integration.
- Own the DV flows including testbench build, regression execution and coverage collection.
- Own emulation and FPGA prototyping build and bring up.
- Build and deploy AI assisted tooling across design and verification workflows, working with CAD and Engineering Infrastructure on compute and model access.
- Keep these flows available through the design cycle, managing tool versions...
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