WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. Backed by Sequoia.
About the role
We are seeking an experienced HDD Servo Processing Subsystem Architecture Lead to join our organization in San Jose, CA, United States. In this pivotal role, you will drive the strategic vision and execution of the servo real-time compute platform architecture—encompassing firmware architecture, instruction set architecture (ISA), and SoC microarchitecture—to enable next-generation HDD products with multiple concurrent data streams and multi-actuator control.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or an equivalent degree and professional experience
- Master's degree or relevant professional certification (e.g., in embedded systems, real-time architecture) desirable
- PhD or specialist certification with demonstrated expertise in real-time, multi-core computing platform architecture highly desirable
- 10+ years of professional experience in embedded architecture and development, with specific focus on real-time control, storage technology, or related servo control applications
- 5+ years of experience as a project technical leader or in senior technical leadership roles, demonstrating strong leadership and commitment to delivering results
- Deep expertise in digital signal processing and real-time systems development
More about this role
We are seeking an experienced HDD Servo Processing Subsystem Architecture Lead to join our organization in San Jose, CA, United States. In this pivotal role, you will drive the strategic vision and execution of the servo real-time compute platform architecture—encompassing firmware architecture, instruction set architecture (ISA), and SoC microarchitecture—to enable next-generation HDD products with multiple concurrent data streams and multi-actuator control. You will be accountable for defining a coherent, scalable platform strategy that balances technical feasibility with economic viability across program schedules, power envelopes, and cost constraints.
- Define and maintain a future-state servo real-time compute architecture and ISA that scales from single to multiple concurrent data streams and supports concurrent control of multiple actuators and heads, with explicit guidance to SoC and servo teams on power, area, and performance trade-offs
- Co-lead SoC microarchitecture decisions affecting servo compute, including core count and placement, memory hierarchy, interconnect design, and dynamic control accelerators, ensuring that FPGA prototype work and accelerator designs map...
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