Alif Semiconductor is revolutionizing the way developers create products using secure 32-bit microcontrollers, with Arm cores for AI/ML acceleration. Backed by Kleiner Perkins and Lightspeed.
About the role
You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology.
What they're looking for
- Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure
- Familiarity with DFT (Tessent) and back-end (Cadence) tools Hands-on experience with digital logic synthesis for power and area optimization
- Experience in low power design issues, tools, and methodology including UPF power intent specification
- Proficient in Verilog/SV/Tcl/Perl/Python
- Highly motivated to debug and resolve CAD tool flow issues
- Self-starter with good analytical, problem solving and communication skills
More about this role
Alif Semiconductor is revolutionizing the way secure connected AI-enabled embedded solutions are created. We are looking for motivated individuals who want to be involved in a fast-paced environment with cutting-edge technology.
You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).
- Run complete synthesis flow
- Define and document synthesis (including DFT insertion) methodology and scripts/flows
- UPF flow for defining power intent (at block and chip level)
- RTL and Netlist hand-off checks (LEC)
- Interface with Physical Design for floor-planning and timing closure
- Assist with design partitioning and floorplan.
- Analyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teams
-...
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