Backed by a16z.
About the role
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge technologies including FPGA, processor, DSP, SERDES, IO, 2.5D/3D multi-die packaging, and other advanced solutions that will drive future innovation. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- 8+ years of experience in DFT design and verification at both RTL and gate level
- Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools
- Design automation experience and proficiency in scripting languages such as Perl/TCL
- Experience with test compression, BIST (MBIST/LBIST), and advanced fault models
- Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT
More about this role
The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge technologies including FPGA, processor, DSP, SERDES, IO, 2.5D/3D multi-die packaging, and other advanced solutions that will drive future innovation.
As a Senior DFT Design Engineer, you will be responsible for DFT architecture and implementation, including DFT specifications, test logic insertion, test mode timing constraints, ATPG, and pre-silicon validation. You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes.
This role provides the opportunity to work closely with IP and integration design teams to understand design and functional behaviors of complex circuits, as well as with test development teams to meet manufacturing test requirements for coverage, cost, yield, and silicon bring-up/debug.
- Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
- Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for...
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