Backed by a16z.
About the role
Altera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of next-generation FPGA and programmable SoC solutions. This is a senior individual-contributor/technical leadership role for an engineer who can influence technical direction across complex subsystems, product generations, and global engineering teams. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Deep hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices
- Strong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems
- Experience leading design execution across multiple functional blocks or chip-level integration, including planning, risk management, schedule alignment, and technical prioritization
- Demonstrated ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product engineering organizations
- Strong written and verbal communication skills, with the ability to clearly communicate architecture, design intent, technical risks, and recommendations to diverse audiences
More about this role
Altera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of next-generation FPGA and programmable SoC solutions. This is a senior individual-contributor/technical leadership role for an engineer who can influence technical direction across complex subsystems, product generations, and global engineering teams.
In this role, you will lead the definition and implementation of high-performance digital logic and reusable IP for programmable devices and platform solutions. You will translate product and system requirements into scalable architectures, drive key design decisions, and guide execution from early concept through RTL delivery, validation, and product readiness. The successful candidate will bring deep experience in complex ASIC, SoC, or FPGA development, a rigorous approach to design quality, and the ability to deliver impactful solutions for data center, networking, AI, and edge applications.
- Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, with emphasis on high-throughput datapaths, connectivity, interconnect, memory...
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