Backed by a16z.
About the role
Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for the verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role will shape verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Demonstrated technical leadership delivering verification for complex digital subsystems or products from architecture through RTL verification, integration, full-chip verification, and hardware or silicon validation
- Deep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking environments, testbench architecture, functional coverage, and coverage-driven closure
- Proven experience creating reusable verification IP, UVM frameworks, testbench components, or methodology adopted across multiple blocks, teams, or programs
- Experience verifying high-performance digital architectures such as networking or packet-processing datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration
- Strong understanding of RTL design, microarchitecture, simulation, debug, formal or static verification concepts, and hardware development flows
- Experience with regression management, simulation build and execution flows, test automation, and data-driven verification reporting
More about this role
Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for the verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role will shape verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations.
In this role, you will define scalable verification strategies, develop reusable verification environments, and drive coverage-driven closure from early architecture through silicon and product readiness. The successful candidate combines deep SystemVerilog/UVM expertise with strong technical judgment, a high bar for verification quality, and the ability to influence engineering execution across global, cross-functional teams.
- Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
- Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives.
- Architect and develop scalable, reusable...
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