Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.
What they're looking for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field
- Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design
- Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity
- Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality
- Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance,...
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