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Physical Design and CAD Engineer

Astera Labs · San Jose, California, United States · On-site

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About Astera Labs

Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.

About the role

As a Physical Design & CAD Engineer , you will serve as a Technical Lead developing Astera Labs’ next-generation connectivity ASICs for cloud and AI infrastructure. This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation. You will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing closure, and GDSII signoff. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, Master's degree preferred
  • 5+ years of experience in ASIC Physical Design, CAD methodology, or design automation
  • Strong understanding of physical design implementation and RTL-to-GDSII methodologies
  • Experience developing or maintaining Physical Design CAD flows
  • Hands-on experience with PNR, timing closure, and physical design signoff
  • Proficiency in Python and/or Tcl scripting
More about this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

As a Physical Design & CAD Engineer , you will serve as a Technical Lead developing Astera Labs’ next-generation connectivity ASICs for cloud and AI infrastructure.

This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation. You will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing...

Read the full posting on Astera Labs's site ↗

ASIC Engineering

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