Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
Astera Labs is seeking a VP of Physical Design to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and UALink technologies. This strategic leadership role will drive the physical implementation of highly complex, multi-die chiplet architectures that are essential to enabling rack-scale AI infrastructure.
What they're looking for
- Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity
- Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs
- Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces
- Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects
- Scale and develop a world-class physical design organization to support aggressive product roadmap
- Manage and mentor Directors, Managers, and senior engineers across the physical design team
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Astera Labs is seeking a VP of Physical Design to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and UALink technologies. This strategic leadership role will drive the physical implementation of highly complex, multi-die chiplet architectures that are essential to enabling rack-scale AI infrastructure. As VP, you will scale and mentor a growing team of...
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