Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
We are looking for a Principal Design Verification Engineer with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred
- ≥8 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
- Knowledge of industry-standard simulators, revision control systems, and regression systems
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Job Overview
We are looking for a Principal Design Verification Engineer with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the...
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