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Principal Digital Design Engineer

Astera Labs · San Jose, California, United States · On-site

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About Astera Labs

Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.

About the role

The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

What they're looking for

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred
  • +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately
  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc
More about this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

  • Strong...

Read the full posting on Astera Labs's site ↗

Design Engineering CCE1

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