Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone.
What they're looking for
- Emulation and Prototyping
- Architect, build, and maintain emulation environments for complex ASICs and SoCs
- Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation
- Enable verification teams to stress-test designs with scalable, repeatable emulation workflows
- Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation
- Protocol and SoC Verification
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Principal Emulation Engineer — San Jose, CA
Role Overview
As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test...
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