Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems.
What they're looking for
- 10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products
- Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc
- Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis
- Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools
- Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology
- Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope)
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration,...
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