Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- Master's degree is preferred
- 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience
- Hands-on experience with Verilog or SystemVerilog RTL development
- Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces
- Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and...
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