Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization
- Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer
- Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies
- Strong scripting and programming skills in Python and/or C/C++ for test automation
- Proven ability to debug complex hardware and firmware issues to root cause
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues.
As AI workloads scale into rack-level infrastructure, every link has to perform...
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