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Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet

Astera Labs · San Jose, California, United States · On-site

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About Astera Labs

Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.

About the role

We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.

What they're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
  • Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification
  • Strong expertise in System Verilog and UVM
  • Extensive experience in verification planning, execution, and sign-off
  • Deep understanding of constrained-random verification and coverage-driven methodologies
  • Strong experience with assertions (SVA), functional coverage, and protocol compliance
More about this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:

We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor...

Read the full posting on Astera Labs's site ↗

Design Verification (DNU) (US_DV_CCE1)

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