Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
About the role
As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Verification Strategy and Planning
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality
- Review designs and verification plans with architecture and RTL teams to identify corner cases early
- Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics
- Environment Development and Execution
More about this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Role Overview
As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.
Within...
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