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Technical Lead Digital Design Engineer

Astera Labs · San Jose, California, United States · On-site

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About Astera Labs

Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.

About the role

Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor’s degree in electrical engineering or equivalent
  • 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
More about this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Overview

Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key...

Read the full posting on Astera Labs's site ↗

ASIC Engineering

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