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ASIC Design Engineer

Broadcom · USA-Colorado-Fort Collins-4380 Ziegler Road · On-site

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About Broadcom

Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.

About the role

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity)
  • Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS)
  • Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff
  • Utilize both commercial and in-house EDA tools for design, implementation, and verification
  • Contribute to design flow improvements, automation, and deep sub-micron methodology development
  • Assist in timing analysis, power planning, IR/EM checks, and post-route optimization
More about this role

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2. If you already have a Candidate Account, please Sign-In before you apply.

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands-on experience with the latest 3 nm and smaller process nodes operating at speeds exceeding 1 GHz, from concept through production. The role offers exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.

Key Responsibilities

  • Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
  • Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).

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Read the full posting on Broadcom's site ↗

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