Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
- Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud ? Come join this team creating devices that accelerate AI/ML workflows ! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.
We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM . You can become a member of an extremely skilled and efficient group of engineers.
This is a rare opportunity to be part of a team that leads products for a new line of devices . The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.
Skills: Self...
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