Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners
- Perform static timing analysis (STA) using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus
- Define and execute timing signoff methodologies, including process corners, derates, and uncertainties
- Conduct pre- and post-route timing analysis, quality of results (QoR) evaluations, and closure verification
- Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners
- Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.
Role Overview
This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes and involves working across multiple design hierarchies to define, validate, and sign off complex timing environments for AI, computing, and networking SoCs.
Key Responsibilities
- Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
- Perform static timing analysis (STA)...
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