Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Extremely proficient in design implementation activities both at block and SoC level
- Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure
- Experience with formal verification, timing analysis and Eco implementation
- Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable
- Full chip tapeout experience based on 7nm and lower technologies is highly preferred
- Good problem solver
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
The candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies to achieve desired PPA metrics. Candidate would also be required to do equivalence checks, STA, Timing closure and power optimization. Should be able to implement timing and functional ECOs.
In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.
Primary expertise in place and route and/ or timing (constraints, STA) can be considered for this position.
- Extremely proficient in design implementation activities both at block and SoC level.
- Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification...
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