Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, SSN etc.)
- Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
- Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will work on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.
- Understanding Broadcom & customer DFT feature requirements
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and...
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