About Broadcom
Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Experience with high-complexity silicon in advanced technology nodes
- Familiarity with timing constraint development for hierarchical designs
- Knowledge of clock tree planning and implementation for SoCs
- Experience with timing ECO creation and final timing signoff
- Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl)
- Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality)
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
- Develop and validate timing constraints for intricate SoC designs.
- Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)
- Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocks
- Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
- Conduct pre-route timing checks and quality of results (QoR) analysis.
- Automate timing analysis processes using scripting languages such as Tcl or Perl.
- Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
- Ensure compliance with timing signoff checklists and criteria.
- Generate timing ECO's for timing closure
- Drive timing closure for complex IP and ASIC blocks
- Experience with high-complexity silicon in advanced technology nodes.
- Familiarity with timing constraint development for hierarchical designs.
- Knowledge of clock...
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