Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
About the role
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What they're looking for
- Architect and design memory subsystems
- Implement RTL of subsystem designs
- Place and route (physical design)
- Design closure: timing, DRC, LVS, EM/IR, etc
- Gate netlist synthesis
- Strong design skills
More about this role
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2. If you already have a Candidate Account, please Sign-In before you apply.
We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 12 years of relevant experience and a Bachelor in Electrical Engineering.
Job Responsibilities
- Architect and design memory subsystems
- Implement RTL of subsystem designs
- Place and route (physical design)
- Design closure: timing, DRC, LVS, EM/IR, etc.
- Gate netlist synthesis
Skill Set Required
- Strong design skills
- Ability to write and debug Verilog RTL code
- Place and route expertise
- Proficient in running STA, DRC, EM/IR tools, and attaining design closure
- Ability to code in Python
- Good understanding of synthesis tools and running synthesis
- Capable of running and debugging logical equivalency checkers
- Familiar with memory behavior
- Proficient in writing automation scripts, and tools savvy
- Good...
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