Cadence delivers remote patient monitoring and chronic disease management that improves outcomes and reduces cost at scale. Intelligent senior care that works better by working ahead. Backed by General Catalyst.
About the role
* Design and integration of IPs in SoC based on high-level architectural specifications from customers. * Perform Lint/CDC checks on the design for quality assurance and resolve related issues. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer
- Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV)
- Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch
- Knowledge of creating synthesis constraints and Static Timing Analysis (STA), familiarity with synthesis tools is a plus
- Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification
- Experience with AMBA protocols and other ARM IPs is a plus
More about this role
* Design and integration of IPs in SoC based on high-level architectural specifications from customers.
* Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
* Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
* Create detailed Microarchitectural Specification documents for the design.
* Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
* Provide support to the physical design team as needed for design implementation.
* Implement innovative solutions to automate repetitive tasks.
* Collaborate within and across teams for effective project execution.
* B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer.
* Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
* Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
* Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
* Familiarity with simulation tools (e.g., Xcelium, Verisium) to support...
Browse similar: Startup jobs