Cadence delivers remote patient monitoring and chronic disease management that improves outcomes and reduces cost at scale. Intelligent senior care that works better by working ahead. Backed by General Catalyst.
About the role
◦ Provide technical support to Cadence customers in Digital Design Implementation and Signoff, including synthesis, floorplanning, placement, clock tree synthesis, routing, design closure, static timing analysis, power integrity, and timing/power signoff. ◦ Lead block, subsystem, or full-chip RTL-to-GDS implementation from synthesized RTL or netlist through final GDS and design-database handoff. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Requires a BS, MS, or PhD in Electrical Engineering or a related field, with 15–17 years of industry experience in design and EDA, focused on Digital Implementation and Signoff
- Deep understanding of the ASIC RTL-to-GDS implementation process and signoff requirements
- Strong hands-on experience with Place and Route tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler
- Experience with synthesis tools such as Cadence Genus or RTL Compiler, or Synopsys Design Compiler
- Experience with EDA tools used in IC digital implementation and signoff flows, including STA tools such as Cadence Tempus or Synopsys PrimeTime
- Strong STA and SDC debugging abilities are required, including MMMC analysis, timing exceptions, OCV-based analysis, clock modeling, SI effects, and implementation-to-signoff correlation
More about this role
◦ The ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their toughest Digital Implementation and Signoff challenges using Cadence technology. The candidate will drive RTL-to-GDS design activities at advanced process nodes using Cadence Digital IC products.
◦ Provide technical support to Cadence customers in Digital Design Implementation and Signoff, including synthesis, floorplanning, placement, clock tree synthesis, routing, design closure, static timing analysis, power integrity, and timing/power signoff.
◦ Lead block, subsystem, or full-chip RTL-to-GDS implementation from synthesized RTL or netlist through final GDS and design-database handoff.
◦ Guide customers on how to best utilize Cadence technologies to achieve PPA, signoff-quality, and project-schedule goals.
◦ Define and review hierarchical implementation strategies, floorplans, voltage areas, macro placement, IO and bump planning, utilization, congestion, and routability objectives.
◦ Drive placement, optimization, CTS, multi-source CTS or clock-mesh implementation, routing, extraction, ECO, and post-route closure.
◦ Own static timing analysis and timing-signoff methodology...
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