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Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions

Cadence · SAN JOSE · On-site

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About Cadence

Cadence delivers remote patient monitoring and chronic disease management that improves outcomes and reduces cost at scale. Intelligent senior care that works better by working ahead. Backed by General Catalyst.

About the role

Join our North America Palladium and Protium HW Development team and help shape the future of system-level chip design verification. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence’s market-leading hardware emulation and FPGA prototyping platforms. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • BS with a minimum of 10 years of experience or MS with a minimum of 7 years of experience
  • Strong fundamentals in digital design, computer architecture, and system‑level verification
  • Have deep technical knowledge in a few of, Simulation (Advanced Testbench), Emulation (TBA & ICE) & FPGA Prototyping
  • Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++
  • Understanding of standard interconnect or IO protocols used in modern chip designs
  • Good debugging skills using waveforms, logs, and protocol analyzers
More about this role

Join our North America Palladium and Protium HW Development team and help shape the future of system-level chip design verification. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence’s market-leading hardware emulation and FPGA prototyping platforms. You will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D — develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers’ most complex architectural and high-Speed Protocol challenges.

  • Customer Enablement & Solutions: Collaborate with frontline engineering teams and customers to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium platforms.
  • Requirements & Feature Development: Define and develop customer-specific emulation and prototyping requirements, focusing heavily on leading edge high-speed interfaces and memory protocols (e.g., PCIe, CXL).
  • Advanced Solutions Engineering: Drive the development of advanced acceleration FW + FPGA system...

Read the full posting on Cadence's site ↗

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