Cerebras powers the world's fastest AI inference on the biggest wafer chip. Cerebras CS-4 delivers up to 30x faster inference than GPUs.
About the role
The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE.
What they're looking for
- Master's/PhD in Computer Science or Electrical Engineering + 1 year industry experience, OR 3+ years industry experience
- Experience in large software environments
- Embedded systems, HW/SW co-design, and some driver development
- Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark, or willingness to learn
- Some network switch environment familiarity or willingness to learn (Arista, Juniper, etc.)
- Detail-oriented but keen to learn the bigger picture and step out of comfort zone to embrace the unknown
More about this role
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As a software developer on the team, you will interface between AI application-level IO teams, cluster architecture teams, and FPGA/ASIC teams to develop solutions that optimize bandwidth and latency while minimizing congestion, pauses, pause...
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