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About the role
As an ASIC Core DFT Technical Lead, you will drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio. You will lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification methodologies.
What they're looking for
- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
- Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design
- Prior experience with Tcl and Python/Perl
More about this role
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
As an ASIC Core DFT Technical Lead, you will drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio. You will lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification...
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