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About the role
We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience
- Experience with ASIC DFT implementation or validation
- Experience with industry DFT tools such as Siemens Tessent , Synopsys DFT Compiler/TestMAX , or equivalent
- Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
- Experience with stuck-at and transition fault models
- Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
More about this role
This is a hybrid role than can be performed three days per week from our San Jose, CA office.
Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.
We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product...
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