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ASIC DFT STA Engineer

Cisco · San Jose, California, US · On-site

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About Cisco

Cisco is a worldwide technology leader powering an inclusive future for all. Learn more about our products, services, solutions, and innovations. Backed by Sequoia and Menlo.

About the role

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
  • Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development
  • Prior working experience in timing constraint development and verification
  • Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile
More about this role

The application window is expected to close on: 12/17/2026

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process...

Read the full posting on Cisco's site ↗

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