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About the role
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor’s degree in Engineering and 15+ years of ASIC related experience, Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience
- Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies
- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
More about this role
The application window is expected to close on: 10/26/2026
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
- Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
- Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
- Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods
- RTL-to-GDSII implementation: Floorplan, Power Grid...
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