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Senior ASIC DFT DV Engineer (Hybrid)

Cisco · San Jose, California, US · On-site

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About Cisco

Cisco is a worldwide technology leader powering an inclusive future for all. Learn more about our products, services, solutions, and innovations. Backed by Sequoia and Menlo.

About the role

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience
  • Prior experience in test planning based on complex design specification
  • Experience debugging using DVE/Verdi
  • Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.​
  • Experience with TCL, Python or Perl
More about this role

The application window is expected to close on: 11/12/2026

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

  • Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
  • Own the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing.
  • Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon.
  • Work with Front-end RTL teams, backend...

Read the full posting on Cisco's site ↗

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