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About the role
• Drives the definition, architecture and design and verification of high performance ASICs • Leads design and DV work by solving block level issues and participates in chip level issue resolution
What they're looking for
- Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 2 years of related experience
- Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools
- Experience with dashboard management for regression, coverage, test list completion and other DV statistics
- Post-silicon lab bring-up experience
- Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
More about this role
The application window is expected to close on: 11/29/2026
This position will require to work onsite 4 days a week in the San Jose location
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
• Drives the definition, architecture and design and verification of high performance ASICs
• Owns complex or multiple functional areas
• Develops reusable code for future projects
• Creates re-usable code
• Debugs at ASIC, SW, HW level
• Works with ASIC and Apps, with limited external scope
• Leads design and DV work by solving block level issues and participates in chip level issue resolution
• Drives reviews...
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