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About the role
Lead the end-to-end characterization flow for standard cell libraries from extracted netlists through Liberty delivery and correlation against TSMC reference data. Define and maintain PrimeLib/Liberate characterization methodology, templates, and automation for timing, power, noise (CCS/NLDM), and leakage across PVT and RC corners.
What they're looking for
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field and 6 years of relevant experience, or Master's Degree and 4 years of experience, or PhD and 1 year of experience
- First-hand experience characterizing standard cell libraries with PrimeLib, Liberate, or equivalent tools
- Strong understanding of Liberty formats (NLDM, CCS, CCS noise, leakage/power modeling) and TSMC (or equivalent foundry) characterization flows
- Experience with parasitic extraction (StarRC or equivalent), LVS, and RC corner / PVT alignment between extraction and characterization
- Solid understanding of CMOS device behavior, timing arcs, power domains, and well/substrate bias effects in deep-submicron nodes
- Preferred Qualifications
More about this role
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.
Lead the end-to-end characterization flow for standard cell libraries from extracted netlists through Liberty delivery and correlation against TSMC reference data.
Define and maintain PrimeLib/Liberate characterization methodology, templates, and automation for timing, power, noise (CCS/NLDM), and leakage across PVT and RC corners.
Drive correlation closure for delay, transition, capacitance, and leakage.
Own extraction-to-char integration: LVS/StarRC setup, RC corner alignment (e.g., cbest_CCbest_T), well-bias port handling (VPP/VBB), and netlist quality gates.
Debug characterization failures at the netlist, simulation, and...
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