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Quantum PDK Design Enablement Engineer

GlobalFoundries · 2 Locations · On-site

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About the role

The Design Enablement Engineer, DRC/LVS/PEX is responsible for developing, qualifying, and deploying physical verification and parasitic extraction components for semiconductor Process Design Kits (PDKs). The role translates complex process and design requirements into accurate, robust, and efficient DRC, LVS, and PEX rule decks and verification flows, while advancing automation and AI/ML-assisted methodologies to improve PDK quality, development efficiency, and customer design success.

What they're looking for

  • Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field
  • Experience: Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level
  • Physical Verification: Experience with DRC and/or LVS rule development, coding, debug, or qualification
  • PEX: Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance
  • Semiconductor Technology: Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions
  • EDA: Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies
More about this role

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

The Design Enablement Engineer, DRC/LVS/PEX is responsible for developing, qualifying, and deploying physical verification and parasitic extraction components for semiconductor Process Design Kits (PDKs). The role translates complex process and design requirements into accurate, robust, and efficient DRC, LVS, and PEX rule decks and verification flows, while advancing automation and AI/ML-assisted methodologies to improve PDK quality, development efficiency, and customer design success.

The Design Enablement Engineer develops and deploys critical PDK components that accurately represent semiconductor manufacturing processes within customer design and verification environments. The engineer will work at the intersection of process technology,...

Read the full posting on GlobalFoundries's site ↗

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