Startups · AI

ASIC Power Engineer, ML Accelerators

Google · United States · On-site

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About Google

Learn more about Google. Explore our innovative AI products and services, and how we. Backed by Kleiner Perkins.

About the role

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 8 years of experience in silicon design or architecture (e.g., logic design, power architecture, performance, or SoC design)
  • Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques
More about this role
  • Contribute to design power modeling and drive convergence to power goals.
  • Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
  • Define best practices and methodologies to achieve low-power designs.
  • Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in silicon design or architecture (e.g., logic design, power architecture, performance, or SoC design).
  • Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience defining and implementing chip-wide power management architectures and designs.
  • Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.
  • Understanding of modern power and thermal management techniques at both the silicon and system levels...

Read the full posting on Google's site ↗

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