Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
About the role
Focus on developing and supporting parasitic extraction flows, with strong hands-on experience in Cadence Quantus and/or Synopsys StarRC, including extraction setup, validation, debugging, post-layout flows. It covers advanced FinFET, BiCMOS, SiGe, and SiPho technologies. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- BSEE with 10–15 years of professional experience, or MS/PhD in Electrical Engineering with 5–10 years of industry experience
- Proven experience building and maintaining analog/mixed-signal design flows for advanced FinFET, BiCMOS, SiGe, and SiPho technologies
- Strong hands-on experience with industry-standard AMS design tools, including Cadence Virtuoso Studio, Synopsys OptoCompiler and Siemens Calibre
- Solid understanding of analog/mixed-signal design flows, including schematic capture, simulation, parasitic extraction, post-layout verification and EMIR
- Programming or scripting experience in Python, TCL, Shell and SKILL
- Experience developing custom CAD automation or verification frameworks
More about this role
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Focus on developing and supporting parasitic extraction flows, with strong hands-on experience in Cadence Quantus and/or Synopsys StarRC, including extraction setup, validation, debugging, post-layout flows. It covers advanced FinFET, BiCMOS, SiGe, and SiPho technologies.
- Architecting and supporting next-generation automated AMS design flows used across Marvell design teams.
- Build and maintain custom tools, PCells, Pycells, GUI utilities, and automation/productivity tools using scripting languages within the Cadence Virtuoso, Synopsys OptoCompiler and Siemens Calibre environments.
- Install, validate, and support foundry PDKs.
- Set up and...
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